1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
As more and more precise technologies are necessary for manufacturing a semiconductor device, the cost of a mask for photolithography used in forming a circuit pattern necessary for performing a desired function increases, and, as a result, the price of a semiconductor chip increases. In order to avoid such a problem of the cost of the mask, a semiconductor chip referred to as a field programmable gate array (FPGA) having a function which is programmable according to the purpose of the chip is sometimes used. The FPGA may perform various functions by changing its circuit configuration with a switch. Typically used as the switch is a static random access memory (SRAM) device including a plurality of transistors. In such device, information on the configured function is lost when the power is shut down, and hence the information on the function needs to be read again when the device is used next time.
On the other hand, for example, an FPGA using an anti-fuse as disclosed in Japanese Patent Application Laid-open No. 2001-28397 prevents loss of the circuit function by fixing the function in the initial stages. An anti-fuse often has a structure in which a pair of electrodes formed in two different wiring layers sandwiches a dielectric. Normally, a dielectric is of high resistance, but, when high voltage is applied between the pair of electrodes, the resistance value of the dielectric makes a high to low transition. By selectively applying high voltage to a specific anti-fuse layer, a desired function may be realized on a gate array.
Japanese Patent Application Laid-open No. 2008-34434 discloses a resistance change device including a metal oxide thin film having reversible variable resistance characteristics. The device has a structure in which a metal oxide containing a transition metal and oxygen is formed between a first electrode and a second electrode, and the resistance value reversibly changes according to a history of voltage applied between the electrodes.
Tzu-Ning Fang, Swaroop Kaza, Sameer Haddad, An Chen, Yi-Ching (Jean) Wu, Zhida Lan, Steven Avanzino, Dongxiang Liao, Chakku Gopalan, Seungmoo Choi, Sara Mandavi, Matthew Buynoski, Yvonne Lin, Christie Marrian, Colin Bill, Michael VanBuskirk and Masao Taguchi, “Erase Mechanism for Copper Oxide Resistive Switching Memory Cells with Nickel Electrode”, IEDM 2006, Session 30-6 proposes a device structure having a resistance change device incorporated therein as a memory device. FIG. 10 is a sectional view illustrating the structure. Lower layer wiring 81, a via plug 82 formed by embedding copper, a resistance change layer 83 formed by forming cuprous oxide Cu2O through oxidation of an uppermost surface of the via plug, and an upper wiring layer 84 which also serves as an upper electrode are provided in the structure. The structure is used as a memory device utilizing a characteristic of Cu2O that, by an electric field applied thereto, the resistance value thereof after the electric field is eliminated changes. The resistance change is reversible, and the resistance value may be changed many times.
However, the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2001-28397 has a problem in a process of patterning the anti-fuse layer immediately above lower wiring. More specifically, when the anti-fuse is patterned immediately above the wiring, the wiring is oxidized by an oxidizing gas used when a photoresist is removed after the patterning.
Further, in the structure disclosed in Tzu-Ning Fang, et al., the upper wiring layer which also serves as the electrode is provided above Cu2O as the resistance change layer. However, if copper wiring formed by a damascene process, which is generally used, is used as the upper wiring layer, a problem arises that, when a wiring groove is formed, the resistance change layer above the via plug is exposed to an etching atmosphere to be damaged or removed.
As described above, it is difficult to form in multilayer wiring a switch element including a resistance change layer having a resistance value which changes by the history of the applied electric field and to suppress damage of the surface of the wiring or of the resistance change layer.